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1 fn6186.3 isl22316 single digitally c ontrolled potentiometer (xdcp?) low noise, low power i 2 c ? bus, 128 taps the isl22316 integrates a s ingle digitally controlled potentiometer (dcp) and n on-volatile memory on a monolithic cmos int egrated circuit. the digitally controlled potent iometer is implemented with a combination of resistor el ements and cmos switches. the position of the wipers are controlled by the user through the i 2 c bus interface. the potentiometer has an associated volatile wiper register (wr) and a non-volatile initial value register (ivr) that can be directly written to and read by the user. the contents of the wr c ontrols the position of the wiper. at power-up, the device recalls the co ntents of the dcps ivr to the wr. the dcp can be used as a three- terminal potentiometer or as a two-terminal va riable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. features ? 128 resistor taps ?i 2 c serial interface - two address pins, up to four devices/bus ? non-volatile storage of wiper position ? wiper resistance: 70 ? typical @ v cc = 3.3v ? shutdown mode ? shutdown current 5a max ? power supply: 2.7v to 5.5v ?50k ?? or 10k ? total resistance ? high reliability - endurance: 1,000,000 data c hanges per bit per register - register data retention: 50 years @ t ? +55 c ? 10 ld msop or 10 ld tdfn package ? pb-free (rohs compliant) pinouts isl22316 (10 ld msop) top view isl22316 (10 ld tdfn) top view 1 2 3 4 5 6 10 9 8 7 sda shdn a0 a1 vcc scl gnd rl rw rh sda shdn a0 a1 vcc scl gnd rl rw rh 1 2 3 4 5 6 10 9 8 7 o ordering information part number (note) part marking resistance option (k ? ) temp. range (c) package (pb-free) pkg. dwg. # isl22316ufu10z* (no longer available, recommended replacement: (isl22316wfrt10z-tk) 316uz 50 -40 to +125 10 ld msop m10.118 ISL22316WFU10Z* 316wz 10 -40 to +125 10 ld msop m10.118 isl22316ufrt10z* (no longer available, recommended replacement: (isl22316wfrt10z-tk) 316u 50 -40 to +125 10 ld 3x3 tdfn l10.3x3b isl22316wfrt10z* 316w 10 -40 to +125 10 ld 3x3 tdfn l10.3x3b *add -tk suffix for tape and reel. please refer to tb347 for details on reel specifications. note: these intersil pb-free plastic packaged products employ sp ecial pb-free material sets, molding compounds/die attach mater ials, and 100% matte tin plate plus anneal (e3 termination finish, which is ro hs compliant and compatible with both snpb and pb-free solderin g operations). intersil pb-free products are msl classified at pb-free peak re flow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. data sheet august 14, 2015 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc 2006, 2008, 2009, 2015. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
2 fn6186.3 august 14, 2015 block diagram power-up interface, control and status logic i 2 c interface v cc rh gnd rl rw scl sda a0 a1 non-volatile registers wr shdn msop pin number tdfn pin number pin name description 1 1 scl open drain i 2 c interface clock input 2 2 sda open drain serial data i/o for the i 2 c interface 3 3 a1 device address input for the i 2 c interface 4 4 a0 device address input for the i 2 c interface 5 5 shdn shutdown active low input 6 6 gnd device ground pin 7 7 rl low terminal of dcp 8 8 rw wiper terminal of dcp 9 9 rh high terminal of dcp 10 10 vcc power supply pin isl22316
3 fn6186.3 august 14, 2015 absolute maximum ratings thermal information storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c voltage at any digital interface pin with respect to gnd . . . . . . . . . . . . . . . . . . . . . -0 .3v to v cc +0.3 v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +6v voltage at any dcp pin with respect to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to v cc i w (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6ma latchup (note 1) . . . . . . . . . . . . . . . . . . class ii, l evel b @ +125c esd ratings human body model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5kv charge device model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1kv thermal resistance (typical) ? ja (c/w) ? jc ( c / w ) 10 lead msop (note 2). . . . . . . . . . . . 162 n/a 10 lead tdfn (notes 3, 4) . . . . . . . . . 74 7 maximum junction temperat ure (plastic package). . . . . . . . +1 50c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp recommended operating conditions temperature range (extended industrial). . . . . . . .-40c to +125c v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7v to 5.5v power rating of each dcp . . . . . . . . . . . . . . . . . . . . . . . . . . . .5mw wiper current of each dcp . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0ma caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 1. jedec class ii pulse conditions and failure criterion used. l evel b exceptions are: using a max positive pulse of 6.5v on th e shdn pin, and using a max negative pulse of -1v for all pins. 2. ? ja is measured with the component mounted on a high effective the rmal conductivity test board in free air. see tech brief tb379 for details. 3. ? ja is measured in free air with the component mounted on a high e ffective thermal conductivity t est board with direct attach f eatures. see tech brief tb379. 4. for ? jc , the case temp location is the center of the exposed metal p ad on the package underside. analog specifications over recommended operating conditi ons, unless otherwise stated. symbol parameter test conditions min (note 19) typ (note 5) max (note 19) unit r total r h to r l resistance w option 10 k ? u option 50 k ? r h to r l resistance tolerance -20 +20 % end-to-end temperature coefficient w option 50 ppm/c (note 18) u option 80 ppm/c (note 18) r w wiper resistance v cc = 3.3v, wiper current = vcc/r total 70 200 ? v rh , v rl v rh and v rl terminal voltages v rh and v rl to gnd 0 v cc v c h /c l /c w (note 18) potentiometer capacitance 10/10/25 pf i lkgdcp leakage on dcp pins voltage at pin from gnd to vcc 0.1 1 a voltage divider mode (0v @ r l ; v cc @ r h ; measured at r w , unloaded) inl (note 10) integral non-linearity monotonic ov er all tap positions, w and u option -1 1 lsb (note 6) dnl (note 9) differential non-linearity monotonic over all tap positions, w a nd u option -0.5 0.5 lsb (note 6) zserror (note 7) zero-scale error w option 0 1 5 lsb (note 6) u option 0 0.5 2 fserror (note 8) full-scale error w option -5 -1 0 lsb (note 6) u option -2 -1 0 tc v (notes 11, 18) ratiometric temperature coeffi cient dcp register set to 40 hex f or w and u option 4 ppm/c isl22316
4 fn6186.3 august 14, 2015 resistor mode (measurements between r w and r l with r h not connected, or between r w and r h with r l not connected) rinl (note 15) integral non-linearity dcp register set between 10 hex and 7f hex; monotonic over all tap positions; w and u option -1 1 mi (note 12) rdnl (note 14) differential non-linearity w option -1 1 mi (note 12) u option -0.5 0.5 mi (note 12) roffset (note 13) offset w option 0 1 5 mi (note 12) u option 0 0.5 2 mi (note 12) analog specifications over recommended operating conditi ons, unless otherwise stated. (continued) symbol parameter test conditions min (note 19) typ (note 5) max (note 19) unit operating specifications over the recommended operating c onditions, unless otherwise spe cified. symbol parameter test conditions min (note 19) typ (note 5) max (note 19) unit i cc1 v cc supply current (volatile write/read) f scl = 400khz; sda = open; (for i 2 c, active, read and write states) 0.5 ma i cc2 v cc supply current (non-volatile write/read) f scl = 400khz; sda = open; (for i 2 c, active, read and write states) 3ma i sb v cc current (standby) v cc = +5.5v @ +85c, i 2 c interface in standby state 5a v cc = +5.5v @ +125c, i 2 c interface in standby state 7a v cc = +3.6v @ +85c, i 2 c interface in standby state 3a v cc = +3.6v @ +125c, i 2 c interface in standby state 5a i sd v cc current (shutdown) v cc = +5.5v @ +85c, i 2 c interface in standby state 3a v cc = +5.5v @ +125c, i 2 c interface in standby state 5a v cc = +3.6v @ +85c, i 2 c interface in standby state 2a v cc = +3.6v @ +125c, i 2 c interface in standby state 4a i lkgdig leakage current, at pins a0, a1, shdn , sda and scl voltage at pin from gnd to v cc, sda is inactive -1 1 a t dcp (note 18) dcp wiper response time scl falling edge of last bit of dcp data byte to wiper new position 1.5 s t shdnrec (note 18) dcp recall time from shutdown mode from rising edge of shdn signal to wiper stored position and rh connection 1.5 s scl falling edge of last bit of acr data byte to wiper stored position and rh connection 1.5 s vpor power-on recall voltage minimum v cc at which memory recall occurs 2.0 2.6 v v cc ramp v cc ramp rate 0.2 v/ms t d power-up delay v cc above vpor, to dcp initial value register recall completed and i 2 c interface in standby state 3ms isl22316
5 fn6186.3 august 14, 2015 eeprom specification eeprom endurance 1,000,000 cycles eeprom retention temperature t ? +55 c 50 years t wc (note 17) non-volatile write cycle time 12 20 ms serial interface specifications v il a1, a0, shdn , sda, and scl input buffer low voltage -0.3 0.3*v cc v v ih a1, a0, shdn , sda, and scl input buffer high voltage 0.7*v cc v cc + 0.3 v hysteresis sda and scl input buffer hysteresis 0.05*v cc v v ol sda output buffer low voltage, sinking 4ma 00.4v cpin (note 18) a1, a0, shdn , sda, and scl pin capacitance 10 pf f scl scl frequency 400 khz t sp pulse width suppression time at sda and scl inputs any pulse narrower than the max spec is suppressed 50 ns t aa scl falling edge to sda output data valid scl falling edge cross ing 30% of v cc , until sda exits the 30% to 70% of v cc window 900 ns t buf time the bus must be free before the start of a new transmission sda crossing 70% of v cc during a stop condition, to sda crossing 70% of v cc during the following start condition 1300 ns t low clock low time measured at the 30% of v cc crossing 1300 ns t high clock high time measured at the 70% of v cc crossing 600 ns t su:sta start condition setup time scl rising edge to sda falling edge; both crossing 70% of v cc 600 ns t hd:sta start condition hold time from sda falling edge crossing 30% of v cc to scl falling edge crossing 70% of v cc 600 ns t su:dat input data setup time from sda exiting the 30% to 70% of v cc window, to scl rising edge crossing 30% of v cc 100 ns t hd:dat input data hold time from scl rising edge crossing 70% of v cc to sda entering the 30% to 70% of v cc window 0ns t su:sto stop condition setup time from scl rising edge crossing 70% of v cc , to sda rising edge crossing 30% of v cc 600 ns t hd:sto stop condition hold time for read, or volatile only write from sda rising edge to scl falling edge; both crossing 70% of v cc 1300 ns t dh output data hold time from scl falling edge crossing 30% of v cc , until sda enters the 30% to 70% of v cc window 0ns t r sda and scl rise time from 30% to 70% of v cc 20 + 0.1*cb 250 ns t f sda and scl fall time from 70% to 30% of v cc 20 + 0.1*cb 250 ns cb capacitive loading of sda or scl total on-chip and off-chip 10 400 pf operating specifications over the recommended operating c onditions, unless otherwise spe cified. (continued) symbol parameter test conditions min (note 19) typ (note 5) max (note 19) unit isl22316
6 fn6186.3 august 14, 2015 notes: 5. typical values are for t a = +25c and 3.3v supply voltage. 6. lsb: [v(r w ) 127 C v(r w ) 0 ] / 127. v(r w ) 127 and v(r w ) 0 are v(r w ) for the dcp register set to 7f hex and 00 hex respectively. l sb is the incremental voltage when changing from one tap to an adjacent t ap. 7. zs error = v(rw) 0 / lsb. 8. fs error = [v(rw) 127 C v cc ] / lsb. 9. dnl = [v(rw) i C v(rw) i-1 ] / lsb-1, for i = 1 to 127. i is the dcp register setting. 10. inl = [v(rw) i C (i ? lsb) C v(rw) 0 ]/lsb for i = 1 to 127 11. for i = 16 to 127 decimal, t = -40c to +125c. max( ) is t he maximum value of the wiper voltage and min ( ) is the minimu m value of the wiper voltage o ver the temperature range. 12. mi = | rw 127 C rw 0 | / 127. mi is a minimum increment. rw 127 and rw 0 are the measured resistances for the dcp register set to 7f he x and 00 hex respectively. 13. roffset = rw 0 / mi, when measuring between rw and rl. roffset = rw 127 / mi, when measuring between rw and rh. 14. rdnl = (rw i C rw i-1 ) / mi -1, for i = 16 to 127. 15. rinl = [rw i C (mi ? i) C rw 0 ] / mi, for i = 16 to 127. 16. for i = 16 to 127, t = -40c to +125c. max() is the maximu m value of the resistance and min () is the minimum value of the resistance over the temperature range. 17. t wc is the time from a valid stop condition at the end of a write sequence of i2c serial interface, to the end of the self-timed internal non-volatile write cycle. 18. limits should be considered ty pical and are not production t ested. 19. parameters with min and/or max limits are 100% tested at +25 c, unless otherwise specified. temperature limits established by characterization and are not production tested. rpu sda and scl bus pull-up resistor off-chip maximum is determined by t r and t f for cb = 400pf, max is about 2k ? ~2.5k ? for cb = 40pf, max is about 15k ? ~20k ? 1k ? t su:a a1 and a0 setup time before start condition 600 ns t hd:a a1 and a0 hold time after stop condition 600 ns operating specifications over the recommended operating conditions, unless otherwise spe cified. (continued) symbol parameter test conditions min (note 19) typ (note 5) max (note 19) unit tc v max v rw ?? i ?? min v rw ?? i ?? C max v rw ?? i ?? min v rw ?? i ?? + ?? 2 ? --------------------------------------------------------------- ------------------------------ - 10 6 +165c -------------------- - ? = tc r max ri ?? min ri ?? C ?? max ri ?? min ri ?? + ?? 2 ? --------------------------------------------------------------- - 10 6 +165c -------------------- - ? = isl22316
7 fn6186.3 august 14, 2015 sda vs scl timing a0 and a1 pin timing t su:sto t dh t high t su:sta t hd:sta t hd:dat t su:dat scl sda (input timing) sda (output timing) t f t low t buf t aa t r t sp t hd:sto t hd:a scl sda a0, a1 t su:a clk 1 start stop figure 1. wiper resistance vs tap position [ i(rw) = v cc /r total ] for 10k ? (w) figure 2. standby i cc vs v cc 0 10 20 30 40 50 60 70 80 90 100 020406080100120 tap position (decimal) v cc = 3.3v, t = +125c v cc = 3.3v, t = +20c v cc = 3.3v, t = -40c wiper resisitance ( ? ) 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 2.7 3.2 3.7 4.2 4.7 5.2 v cc (v) i sb (a) t = +25c t = +125c isl22316
8 fn6186.3 august 14, 2015 figure 3. dnl vs tap position in voltage divider mode for 10k ? (w) figure 4. inl vs tap position in voltage divider mode for 10k ? (w) figure 5. zs error vs temperature figure 6. fs error vs temperature figure 7. dnl vs tap position in rheostat mode for 10k ? (w) figure 8. inl vs tap position in rheostat mode for 10k ? (w) typical performance curves (continued) dnl (lsb) -0.2 -0.1 0 0.1 0.2 0 20406080100120 tap position (decimal) t = +25c v cc = 5.5v v cc = 2.7v -0.2 -0.1 0 0.1 0.2 0 20 40 60 80 100 120 tap position (decimal) inl (lsb) t = +25c v cc = 5.5v v cc = 2.7v -0.3 -0.1 0.1 0.3 0.5 0.7 0.9 1.1 1.3 -40 -20 0 20 40 60 80 100 120 temperature (c) zs error (lsb) v cc = 5.5v v cc = 2.7v 50k 10k -1.5 -1.2 -0.9 -0.6 -0.3 0.0 -40 -20 0 20 40 60 80 100 120 temperature (oc) zs error (lsb) v cc = 5.5v v cc = 2.7v 50k 10k -0.6 -0.4 -0.2 0 0.2 0.4 16 36 56 76 96 116 tap position (decimal) dnl (lsb) t = +25c v cc = 2.7v v cc = 5.5v -0.6 -0.4 -0.2 0 0.2 0.4 16 36 56 76 96 116 tap position (decimal) inl (lsb) t = +25c v cc = 2.7v v cc = 5.5v isl22316
9 fn6186.3 august 14, 2015 figure 9. end-to-end r total % change vs temperature figure 10. tc for voltage divider mode in ppm figure 11. tc for rheostat mode in ppm figure 12. frequency respon se (2.6mhz) figure 13. midscale glitch, code 3fh to 40h figure 14. large signa l settling time typical performance curves (continued) -1.0 -0.5 0.0 0.5 1.0 -40 -20 0 20 40 60 80 100 120 temperature (oc) end to end r total change (%) 50k 10k v cc = 5.5v v cc = 2.7v 0 15 30 45 60 75 90 105 16 36 56 76 96 tap position (decimal) tcv (ppm/c) 50k 10k tcr (ppm/c) 0 50 100 150 200 250 300 16 36 56 76 96 tap position (decimal) 50k 10k output input wiper at mid point (position 40h) r total = 9.5k ? ??? ???? ???? ??? ??? ???? ???? isl22316
10 fn6186.3 august 14, 2015 pin description potentiometers pins rh and rl the high (rh) and low (rl) te rminals of the isl22316 are equivalent to the fixed t erminals of a mechanical potentiometer. rh and rl are r eferenced to the relative position of the wiper and not the voltage potential on the terminals. with wr set to 12 7 decimal, the wiper will be closest to rh, and with the wr s et to 0, the wiper is closest to rl. rw rw is the wiper terminal and i s equivalent t o the movable terminal of a mechanical potenti ometer. the position of the wiper within the array is det ermined by the wr register. shdn the shdn pin forces the resistor to end-to-end open circuit condition on rh and shor ts rw to rl. when shdn is returned to logic high, the prev ious latch settings put rwi at the same resistance setting pr ior to shutdown. this pin is logically and with the shdn bit in the acr register. the i 2 c interface is still available in shutdown mode and all registers are accessible. this pin mu st remain high for normal operation. bus interface pins serial data input/output (sda) the sda is a bidirectional seri al data input/output pin for i 2 c interface. it receives device address, operation code, wiper address and data from an i 2 c external master device at the rising edge of the serial clock scl, and it shifts out data aft er each falling edge of the serial clock. sda requires an external pull-up resistor, since it is an open drain input/output. serial clock (scl) this input is the serial clock of the i 2 c serial interface. scl requires an external pull-up resistor, since it is an open drai n input. device address (a1, a0) the address inputs are used to s et the least significant 2 bits of the 7-bit i 2 c interface slave address. a match in the slave address serial data stream must match with the address input pins in order to initiate communication with the isl22316. a maximum of four isl22316 devices may occupy the i 2 c serial bus. principles of operation the isl22316 is an integrated circuit incorporating one dcp with its associated registers, non-volatile memory and an i 2 c serial interface providing di rect communication between a host and the potentiometer and memory. the resistor array is comprised of individual res istors connected in series. at either end of the a rray and between eac h resistor is an electronic switch that transfers the potential at that point to the wiper. the electronic switches on the device operat e in a make before break mode when the w iper changes tap positions. when the device is powered dow n, the last value stored in ivr will be maintained in the non-volatile memory. when power is restored, the contents of the ivr is recalled and loaded into the wr to set the wiper to the initial value. dcp description the dcp is implemented with a combination of resistor elements and cmos switches. the physical ends of each dcp are equivalent to the fix ed terminals of a mechanical potentiometer (rh and rl pins). the rw pin of the dcp is connected to i ntermediate nodes, and is equivalent to the wiper terminal of a mechanica l potentiometer. the position of the wiper terminal within the dcp is controlled by a 7-bit volatile wiper register (wr ). when the wr of a dcp contains all zeroes (wr<6:0>: 00h), its wiper terminal (rw) is closest to its low terminal (rl). when the wr register of a dcp contains all ones (wr<6:0>: 7fh), its wiper terminal (rw) is closest to its high terminal (rh). as the value of the wr increases from all zeroes (0) to all ones (127 decimal), the wiper moves mon otonically from the position closest to rl to the closest t o rh. at the same time, the resistance between rw and rl increases monotonically, while the resistance bet ween rh and rw decreases monotonically. while the isl22316 is being pow ered up, the wr is reset to 40h (64 decimal), which locat es rw roughly at the center between rl and rh. after the power supply voltage becomes large enough for re liable non-volatile memory reading, the wr will be reloa d with the val ue stored in a non-volatile initial value register (ivr). the wr and ivr can be read or written to d irectly using the i 2 c serial interface as describ ed in the following sections. memory description the isl22316 contains one non-vo latile 8-bit register, known as the initial value register ( ivr), and two volatile 8-bit registers, wiper register (wr) and access control register (acr). table 1 shows the memory map of the isl22316. the rl rw rh figure 15. dcp connection in shutdown mode isl22316
11 fn6186.3 august 14, 2015 non-volatile register (ivr) at a ddress 0, contain initial wiper position and volatile registers (wr) contain current wiper position. the non-volatile ivr and vo latile wr registers are accessible with th e same address. the access control register ( acr) contains information and control bits described in table 2. the vol bit (acr<7>) determi nes whether the access is to wiper registers wr or ini tial value registers ivr. if vol bit is 0, the non-volatil e ivr register is accessible. i f vol bit is 1, only the volatile w r is accessible. note, value is written to ivr register als o is written to the wr. the default value of t his bit is 0. the shdn bit (acr<6>) disabl es or enables shutdown mode. this bit is logically and with shdn pin. when this bit is 0, dcp is in shutdown mode. defaul t value of shdn bit is 1. the wip bit (acr<5> ) is read only bit. it indicates that non-volatile write operation is in progress. it is impossible t o write to the wr or acr while wip bit is 1. shutdown mode the device can be put in shutdown mode either by pulling the shdn pin to gnd or setting the shdn bit in the acr register to 0. the truth table for s hutdown mode is in table 3. i 2 c serial interface the isl22316 supports an i 2 c bidirectional bus oriented protocol. the pr otocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. the device controlli ng the transfer is a master and the device being controlled is the slave. the master always initiates data transfers and provides the clock for both transmit and receive operati ons. therefore, the isl22316 operates as a slave device in all applications. all communication over the i 2 c interface is conducted by sending the msb of eac h byte of data first. protocol conventions data states on the sda lin e must change only during scl low periods. sda state cha nges during scl high are reserved for indicating st art and stop conditions (see figure 16). on power-up of the isl22316, the sda pin is in the input mode. all i 2 c interface operations m ust begin with a start condition, which is a high to l ow transition of sda while scl is high. the isl22316 continuously monitors the sda and scl lines for the start condition and does not respond to any command until this condition is met (see figure 16). a start condition is ignored during the power-up of the device. all i 2 c interface operations must be terminated by a stop condition, which is a low to h igh transition of sda while scl is high (see figure 16). a stop condition at the end of a read operation, or at the end of a write operation places the device in its standby mode. an ack, acknowledge, is a so ftware convention used to indicate a successful data tran sfer. the transmitting device, either master or slave, re leases the sda bus after transmitting eight bits. duri ng the ninth cl ock cycle, the receiver pulls the sda line low to acknowledge the reception of the eight bit s of data (see figure 17). the isl22316 responds with an ack after recognition of a start condition followed by a v alid identificat ion byte, and once again after succe ssful receipt of an address byte. the isl22316 also responds with an ack after receiving a data byte of a write ope ration. the master must respond with an ack after receiving a data byte of a read operation a valid identification byte con tains 01010 as t he five msbs, and the following two bits matching the logic values present at pins a1 and a0. the lsb is the read/write bit. its value is 1 for a read ope ration, and 0 for a write operation (see table 4). table 1. memory map address non-volatile volatile 2 acr 1 reserved 0ivr wr table 2. access control register (acr) vol shdn wip 00000 table 3. shdn pin shdn bit mode high 1 normal operation low 1 shutdown high 0 shutdown low 0 shutdown 01010a1a0r/w (msb) (lsb) table 4. identification byte format logic values at pins a1 and a0 respectively isl22316
12 fn6186.3 august 14, 2015 sda scl start data data stop stable change data stable figure 16. valid data changes, start and stop conditions sda output from transmitter sda output from receiver 8 1 9 start ack scl from master high impedance figure 17. acknowledge response from receiver high impedance s t a r t s t o p identification byte address byte data byte a c k signals from the master signals from the slave a c k 00 0 11 a c k write signal at sda 0000 a0 a1 0 figure 18. byte write sequence 0 signals from the master signals from the slave signal at sda s t a r t identification byte with r/w = 0 address byte a c k a c k 00 0 11 s t o p a c k 1 identification byte with r/w = 1 a c k s t a r t last read data byte first read data byte a c k 0 000 a0 a1 a0 a1 figure 19. read sequence a c k 0 0 010 1 isl22316
13 fn6186.3 august 14, 2015 write operation a write operation requires a start condition, followed by a valid identification byte, a valid addre ss byte, a data byte, and a stop condition. after each of the three bytes, the isl22316 responds with an ack . at this time, the device enters its standby st ate (see figure 18). the non-volatile write cycle st arts after stop condition is determined and it requires up t o 20ms delay for the next non-volatile write. read operation a read operation consists o f a three byte instruction followed by one or more data bytes (see figure 19). the master initiates the opera tion issuing the following sequence: a start, the identif ication byte with the r/w bit set to 0, an addre ss byte, a second sta rt, and a second identification by te with the r/w bit set to 1. after each of the three bytes, t he isl22316 responds with an ack. then the isl22316 transmits data b ytes as long a s the master responds with an ac k during the scl cycl e following the eighth bit of each byte. th e master terminates the read operation (issuing a ack and stop condition) following the last bit of the last data byte (see figure 19). in order to read back the non-volatile ivr, it is recommended that the application r eads the acr first to verify the wip bit is 0. if the wip bit ( acr[5]) is not 0, the host should repeat its reading sequence again. isl22316
14 all intersil u.s. products are m anufactured, assembled and test ed utilizing iso9001 quality systems. intersil corporations quality ce rtifications can be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products , see www.intersil.com fn6186.3 august 14, 2015 about intersil intersil corporation is a leading provider of innovative power management and precision analog solutions. the company's produc ts address some of the largest marke ts within the industrial and i nfrastructure, mobile computing and high-end consumer markets. for the most updated datasheet, application no tes, related documentation and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggesti ons for improving this datashe et by visiting www.intersil.com/ask . reliability reports are also a vailable from our website at www.intersil.com/support revision history the revision history provided is for informational purposes onl y and is believed to be accurate, but not warranted. please go to the web to make sure that you have the latest revision . date revision change august 14, 2015 fn6186.3 - ordering information table on page 1. - added revision history beginning with rev 1. - added about intersil verbiage. -updated l10.3x3b to most recent revision, changes are as follo ws: -revision 0 to revision 1 changes: removed from jedec format to c omply with new standards. changes include: removed table and put dimensions on package outline drawing ins tead added typical recommended land pattern note "dimension b applies to t he metallized terminal and is mea sured between 0.15mm and 0.30mm from the terminal tip." changed to "dimension b applies to the metallized terminal and is measured between 0.18mm and 0.30mm from the terminal tip. -revision 1 to revision 2 changes: 1. removed mention of "b" from note 4 since "b" does not exist on the drawing. 2. added note 6 callout to lead width on "bottom view" 3. corrected the word "indentifier" in note 6 to read "identifi er" -revision 2 to revision 3 changes: removed package outline and included center to center distance between lands on recommended land pattern. removed note 4 "dimension b appl ies to the metallized terminal and is measured between 0.18mm and 0.30mm from the terminal tip. " since it is not applicable t o this package. renumbered notes accordingly. -revision 3 to revision 4 tiebar note updated from: tiebar shown (if present) is a non-functional feature. to: tiebar shown (if present) is a non-functional feature and m ay be located on any of the 4 sides (or ends -updated pod m10.118 to most cur rent version change is as follo ws: added land pattern. isl22316
15 fn6186.3 august 14, 2015 isl22316 package outline drawing l10.3x3b 10 lead thin dual flat package (tdfn) with e-pad rev 4, 4/15 located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 the configuration of the pin #1 identifier is optional, but mus t be dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 5. either a mold or mark feature. 3. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" side view typical recommended land pattern top view (4x) 0.15 index area pin 1 pin #1 index area c seating plane 0.08 see detail "x" c c 4 5 5 a b 0.10 c 2 6 10 1 0.75 0.05 0.50 2.38 +0.1/ - 0.15 3.00 (10x0.25) (8x 0.50) 2.38 1.64 (10x0.60) 3.00 0.05 0.20 ref 0.25 +0.05/ - 0.07 10x 0.40 +/- 0.1 1.64 +0.1/ -0.15 2.80 typ tiebar shown (if present) is a non-functional feature and may be located on any of the 4 sides (or ends).
16 fn6186.3 august 14, 2015 isl22316 package outline drawing m10.118 10 lead mini small outline plastic package rev 1, 4/12 detail "x" side view 2 typical recommended land pattern top view pin# 1 id 0.18 - 0.27 detail "x" 0.10 0.05 (4.40) (3.00) (5.80) h c 1.10 max 0.09 - 0.20 33 gauge plane 0.25 0.95 ref 0.55 0.15 b 0.08 c a-b d 3.00.05 12 10 0.85010 seating plane a 0.50 bsc 3.00.05 4.90.15 (0.29) (1.40) (0.50) d 5 5 side view 1 dimensioning and tolerancing conform to jedec mo-187-ba plastic interlead protrusions of 0.15mm max per side are not dimensions in ( ) are for reference only. dimensions are measured at datum plane "h". plastic or metal protrusions of 0.15mm max per side are not dimensions are in millimeters. 3. 4. 5. 6. notes: 1. 2. and amsey14.5m-1994. included. included. 0.10 c m

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